Embodiments of the present invention are generally related to photolithography for the manufacture of semiconductor devices. More particularly, embodiments of the present invention provide combination test patterns used for photolithography process tuning and monitoring.
The minimum feature sizes of integrated circuits (ICs) have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography.
Photolithography involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers.
An integral component of photolithographic apparatus is a “reticle” which includes a pattern corresponding to features at one layer in an IC design. The reticle typically includes a transparent glass plate covered with a patterned light blocking material such as chromium. The reticle is placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens, which may form part of a “stepper” apparatus. Placed beneath the stepper is a resist covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, light passes through the glass (regions not having chromium patterns) projects onto the resist covered silicon wafer to produce photo-generated acid. The resist is typically baked to undergo chemical changes that alter its dissolution properties. Subsequent development process is needed to obtain the relief image on wafer. In this manner, an image of the reticle is transferred to the resist.
As light passes through the reticle, it is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. Furthermore, resist processing effects during the bake process, such as nonlinear diffusion of the photo-generated acid, exacerbate the pattern distortion on the wafer. Subsequent pattern transfer processing effects, such as etch bias, further degrade the pattern fidelity. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they cannot be ignored in layouts having features smaller than about 1 micron. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process. Recent semiconductor devices have scaled down to 60 nm.
To remedy this problem, a reticle correction technique known as optical proximity correction (OPC) has been developed. Optical proximity correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated with software to identify regions where optical distortion will result. Then the optical proximity correction is applied to compensate for the distortion. The resulting pattern is ultimately transferred to a reticle glass.
Conventional lithography processes including OPC techniques suffer from many drawbacks, some of which are described below. Therefore, there is a need for improve techniques that can improve OPC effectiveness and photolithography process tuning and monitoring.